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Partitioning Complex Logic Networks With Structured Design for Test Purposes Disclosure Number: IPCOM000062121D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

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Dittus, B [+details]


For automatically generating test patterns for logic networks, the computing time is proportional to a value exceeding the square value of the number of logic gates. Therefore, the computing times required for generating the test patterns for a VLSI network are excessive. However, to permit testing such networks, the above circuit is inserted at one point or several points of the network. Line A, previously leading straight to A OUT, is now connected to input 1 of an AND-OR gate 2, output A OUT of which is linked to a further gate (not shown) in the network portion to the right of the inserted circuit and to data input D of a master-slave latch 3.