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Dense Sense Amplifier/Latch Combination

IP.com Disclosure Number: IPCOM000062125D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Loehlein, WD Tong, MH [+details]

Abstract

A modified sense amplifier is proposed that can act both as a sense amplifier and as a data-out latch. This effect is obtained by controlling the sense amplifier, using two signals which enable the merged sense amplifier/latch function. Fig. 1 is the diagram of a data path with a symbolically indicated memory cell for an array, as well as a flip-flop configuration T1 to T4 as a sense amplifier/latch combination. In the illustrated example, T1 and T2 designate an N-channel FET and T3 and T4 a P-channel FET complementary thereto. Other transistor combinations are, of course, equally conceivable. The word line and the bit lines (true and complement) are designated as WL, BLT and BLC. The further circuit elements will be referred to below.