Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
A circuit is described by which current peaks, occurring during the power-on of DRAM (dynamic random-access memory) chips, are avoided. This eliminates overdimensioned power supplies and the provision of decoupling capacitors on circuit boards, as well as power sequencing. DRAM chips use the electric charge of small capacitors (cell capacitors) for storing data. In the off state (chip power off), these capacitors are discharged. However, when the supply voltage is switched on, they are abruptly charged in an uncontrolled manner, as the control signals have undefined levels in the absence of the full supply voltage.