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Functional Fault-Correction Method of Cache And/Or Directory Arrays Disclosure Number: IPCOM000062129D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

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Boudon, G Mollier, P Yamour, Y [+details]


In large chips, multiple word/bit redundancy techniques are used, at the chip level, in order to detect and correct faults in memory arrays. This technique consists of having spare decoders, words and bit lines in order to replace defective lines at these addresses. This type of redundancy technique can improve the chip yield, at the price of hardware overhead and performance penalty. The cost of that redundancy is estimated as a 10% overhead of that function's overall hardware, along with a performance degradation. In the case of a Cache system, this performance impact can pose a problem, since it impacts the machine's most critical timing machine cycle path.