Browse Prior Art Database

Very High Speed Adders With Cascode Differential Circuits

IP.com Disclosure Number: IPCOM000062132D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Boudon, G Tannhof, P [+details]

Abstract

Previously there was shown the excellent speed power product of the cascode circuits when compared to the traditional NAND gates in a master slice. This advantage is due to the fact that a complex function can be implemented in only one logic tree either with differential or single-ended circuits. The present disclosure describes an application with an Adder where the usage of the differential cascode circuit also gives a good speed power product. As an example, a 64-bit adder is described, with a sum which can be done in 4 cascode tree delays with 5 levels of bipolar or FET transistors. The design of a very high speed Adder - Subtractor is possible with the carry calculation made in a parallel mode in a look-ahead carry circuit. The table below is a truth table for the sum and the carry of 2 bits A and B with a carry in.