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Punch-Through Guard Ring for Butted Transistor Emitters

IP.com Disclosure Number: IPCOM000062134D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Cressler, JD [+details]

Abstract

This article relates generally to semiconductor fabrication and, more particularly, to construction of guard rings for butted emitters to prevent punch-through. A single added implantation step during fabrication of NPN transistors having butted emitters produces a thicker guard ring to prevent emitter-collector punch-through. The construction process is as follows: In Fig. 1, layers of silicon dioxide 1 and silicon nitride 2 are deposited on silicon substrate 3. Photoresist 4 is deposited, exposed and developed to define the active device region. Boron implantation is performed through layers 1 and 2 and produces "transverse straggle" in areas 5 to form the guard ring beneath layer 1 and the mask opening. In Fig.