Browse Prior Art Database

N WELL Contact for CMOS Gate Array With Silicide and Deep Trench Process

IP.com Disclosure Number: IPCOM000062135D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Boudon, G Mollier, P Nuez, JP Vallet, V Wallart, F [+details]

Abstract

In some applications, it may happen that the manufacturing process was initially aimed at producing 'N' MOS transistors only. Its extension to CMOS and CMOS gate arrays, may raise some difficulties in the realization of N WELL contacts. This article describes a structure which permits having a good N WELL contact to the VDD power supply with an advanced CMOS technology using a deep trench and silicide. With the sub-micron channel length CMOS, the deep trench improves the latch-up immunity, while the silicide reduces the serial resistance of the poly and the drain or source diffusions. The structure for an N WELL contact in a traditional CMOS gate array cannot be used, due to the silicide which shorts all the elements in a diffusion area and due to the deep trench which splits the N WELL diffusion in two parts. Fig.