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Linear Addressing of I/O Hierarchies in Computer Architecture Disclosure Number: IPCOM000062154D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

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Related People

Bourke, DG Downs, ES Kurtz, HL [+details]


A technique is described whereby computer architecture is enhanced through the use of linear addressing of input/output (I/O) hierarchies. Also described is the interpretation and the use of logical I/O address formatting within the hierarchical tree and the use of an I/O address format that supports addressing within a hierarchical-tree-structured I/O configuration that may be unbalanced. The format eliminates the need for a table look-up, which are normally used to determine which intermediate facilities in the hierarchy are in the routing path of the target device.