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Thin Film Field-Effect Transistor

IP.com Disclosure Number: IPCOM000062156D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Bumble, B Gallagher, WJ [+details]

Abstract

A submicron self-aligned FET is constructed in which the source-drain electrode separation is defined by a film thickness and is in the range of N 0.2 mm. The gate electrode is self-aligned to the channel separating the electrodes and covers all the channel. All critical dimensions and alignments are defined by film thicknesses. The structure is shown in Fig. 1, in which the gate region has been extended by a metallic cap placed over the bevelled edge of the trilayer prior to the deposition of the gate insulation and semiconductor layers. In this structure conductivity of the entire semiconducting region between the source and drain contact electrodes is effectively modulated by the potential placed on the gate electrode-- there is a large difference between the "on" and "off" resistance of FETs with this structure.