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Optimized Chip Layout Using Expandable Unit Cell Design

IP.com Disclosure Number: IPCOM000062162D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Edelman, A Stoops, CA [+details]

Abstract

A technique is described whereby circuit macros, as used in very large scale integrated (VLSI) master-image and masterslice processes, are optimized in the circuit chip layout so as to reduce the amount of total area on a typical circuit chip. Expandable unit cells and stretch lines are utilized to obtain the optimization. In prior art, the use of circuit macros in VLSI master-image and masterslice technologies required the use of predetermined wiring bays to be placed between the circuit macros. This created wasted space, as shown in Fig. 1, and caused wiring channels to be unused in some areas, while other areas had a shortage of channels. This caused an inefficient utilization of space and required additional circuit chips to be used.