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Cryogenic Tunneling Transistor

IP.com Disclosure Number: IPCOM000062165D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Kleinsasser, AW Woodall, JM [+details]

Abstract

A cryogenic transistor device is provided wherein control of current through a tunnel barrier is achieved through gate control of the barrier height. The structure includes a compatible barrier material which can be fabricated by readily available techniques. The structure is illustrated in Fig. 1, along with the band structure of the active region in Fig. 2. The basis of the structure is the edge of a multilayer sandwich of thin films consisting of metal, insulator, metal, insulator. Such a sandwich can be formed by ion beam or plasma etching. As an example, a Nb film is deposited and anodized, followed by a second Nb deposition and anodization. The edge is then formed by plasma etching in CF4/O2 . After the edge is formed, a counterelectrode pattern is defined with photoresist.