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Process for Realizing CTS Cell Arrays With Improved Density and Performance

IP.com Disclosure Number: IPCOM000062171D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Jambotkar, CG [+details]

Abstract

Disclosed is a method of making compact complementary transistor switch (CTS) cells for use in semiconductor devices. Array performance of the cross-coupled PNPN devices is improved with this approach. Referring to Fig. 1, starting with a P- substrate, an N+ subcollector 4 is formed, followed by an N- epitaxial layer 8, an epi reox SiO2 layer 10, recessed oxide isolation (ROI) 12 and N+ reach through, all achieved in a conventional manner. Polysilicon 14 and Si3N4 16 are deposited with a P+ type dopant ion-implanted into the polysilicon. An appropriate mask is used to pattern the composite of nitride and polysilicon through reactive ion etching (RIE). RIE is continued to etch the exposed SiO2 layer 10 employing a resist mask; SiO2 10 is then undercut by about 0.3 mm, as shown at 18 in Fig. 2.