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Two-Stage Decoder for Static Rams

IP.com Disclosure Number: IPCOM000062188D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Clemen, R Haug, W Helwig, K Loehlein, WD [+details]

Abstract

This article describes a 1-of-2**n decoder, as is required, for example, for address decoding in random-access memories (RAMs), and in particular a static CMOS row or column decoder. Fig. 1 shows a CMOS implementation of the second stage of the two- stage decoder, and Fig. 2 a CMOS embodiment of such a two-stage decoder using a final two-way logic gate which provides the -*Y function. In the circuit of Fig. 2, - and Y are ANDed by the input inverter, the X signal being connected to the gates of transistors TP1 and TN1 and the Y signal being fed to the source of the PFET load TP1. After selection with X low and Y high, this final decoder (in contrast to a clocked/dynamic approach) can be switched to the half- selected mode if Y goes down and X remains low.