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High Density Vertical DRAM Cell

IP.com Disclosure Number: IPCOM000062209D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Hwang, W Terman, LM [+details]

Abstract

This article describes a new high density vertical trench DRAM (dynamic random-access memory) cell. The cross section of two adjacent DRAM cells is shown in Fig. 1 together with its schematic layout (Fig.2) and circuit diagram (Fig. 3). The transfer device is oriented in the vertical direction and is positioned over the trench storage capacitor. A shallow trench filled with polysilicon or polycide (e.g., poly-Si, WSi2, and Si) serves as the MOS transfer device gate. Transfer MOSFETs of adjacent cells share the same gate. Arrangement of the trench stor age capacitors and transfer devices are different from those of the conventional planar and trench DRAM cells. By placing the transfer device in a vertical orientation over the trench capacitor, cell area can be reduced. A cell layout is shown in Fig. 2.