Browse Prior Art Database

Sidewall Spacer Construction

IP.com Disclosure Number: IPCOM000062211D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Harame, DL [+details]

Abstract

This article relates generally to integrated circuit fabrication and, more particularly, to a process for forming sidewall spacers. Non- conforming silicon evaporation and rapidly etched phosphorous glass enable more efficient and precise construction of bipolar devices. Referring to Fig. 1, nitride layer 1 is evaporated onto oxide layer 2 formed by a recessed oxide process on substrate 3. Boron phosphorous glass (BPSG) 4 is then evaporated onto the nitride layer in sufficient thickness for subsequent lift-off. Glass 4 is annealed and photoresist is deposited, exposed and developed to form the intrinsic base and emitter opening 5 with BPSG thereon. Reactive ion etching (RIE) removes the BPSG and nitride outside base and emitter region 5.