Browse Prior Art Database

Alternate I/O Addressing for Coprocessor Basic I/O System

IP.com Disclosure Number: IPCOM000062280D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Buckland, PA [+details]

Abstract

A method is described which allows a coprocessor to separately trap BIOS (Basic Input/Output System) I/O instructions and non-BIOS I/O instructions to selected I/O devices. Most Personal Computer (PC) I/O devices can be accessed through multiple addresses. The programmers generally treat undecoded address bites as zero, so that an I/O address of 'x3F0' hex is programmed as '03F0' hex, but an alternate I/O address, such as '13F0', '23F0', or F3F0' hex, can be used. Where the coprocessor I/O trap logic uses the high-order 13 bits of a 16-bit I/O address, and can differentiate between an I/O access of '13F0', '23F0',.....,'F3F0' hex and '03F0' hex, the trap logic can be used to differentiate between a BIOS and a non-BIOS access to an I/O device when the coprocessor BIOS uses alternate I/O addresses.