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Planar Buried Contact Heterojunction FET

IP.com Disclosure Number: IPCOM000062292D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Kuech, TF Rupprecht, HS Theis, TN [+details]

Abstract

Through the use of ion implantation plus the in situ annealing and etching involving MOCVD the fabrication of a heterojunction FET with relaxed lithographic tolerances is achieved. A GaAs gated, or modulation doped Schottky gated, heterojunction FET is provided with a short channel achieved with relaxed lithographic tolerances. Source and drain regions of a GaAs substrate are doped by ion implantation or possibly diffusion. In situ annealing and surface etching using a MOCVD reactor prepare the substrate for subsequent growth of AlGaAs and n+ GaAs heterolayers. Processing steps are illustrated in connection with the figures. (Image Omitted) Ion-implanted wafer with source and drain contact regions supplied.