Browse Prior Art Database

Microprocessor Buffer Caching

IP.com Disclosure Number: IPCOM000062313D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Hughes, DR Sawtschenko, AP Storm, CL [+details]

Abstract

This article describes an apparatus and method for processing data generated from terminals connected to a loop communications network. A single shared buffer is used to store data from the terminals. The shared buffer is normally controlled by a dedicated microprocessor. The dedicated microprocessor periodically allows the main processor to access the buffer. During the intervals when the main processor is accessing the shared buffer, a cache memory which may be internal to the dedicated microprocessor is used for storing data from the terminals. The figure shows the caching operation for two processors sharing a single buffer. The legends at the right hand side of the diagram identify the components and/or action taken at a particular instant of time.