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Addition of Chip Test Features Without Adding Module Pins

IP.com Disclosure Number: IPCOM000062328D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Pontius, D [+details]

Abstract

A voltage level not available in normal circuit operation, applied to regular input pads, is used to activate test features built into a circuit chip, such as a large random-access memory (RAM). In addition, a decode register is employed to access a very large number of test mode option control bits. A decode register utilizing some already existing input buffer lines as addresses and others as data for test feature registers is described for use when the required number of test feature option bits exceeds available input buffer lines. Referring to the figure, a test feature register write signal 2 is generated by a circuit such as the one described in [*]. Signal 2 is entered into the 1-of-4 decode register 4, thus activating the test mode.