CMOS Toggle Flip-Flop
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
A CMOS toggle flip-flop circuit design is presented which uses less than one-half the number of devices used in a conventional toggle flip-flop. A static edge-triggered flip-flop design is shown in Fig. 1 and a timing chart for the circuit is shown in Fig. 2. The circuit can be initiated by either pulsing the CLEAR line or the PRESET line while CLOCK is low, depending on the polarity of output initially desired. By pulsing the CLEAR line, T17 is turned on and output Q (node E) is pulled down. When node E is pulled down, T13 turns on, T14 turns off and node F goes high. With CLOCK low and not CLOCK high, pass devices T1 and T2 and T9 and T10 are set off and pass devices T7 and T8 and T15 and T16 are set on. When devices T15 and T16 are on, output data line not Q (node D) is pulled high.