Browse Prior Art Database

Selective Word Transfer on Cross-Interrogation Castouts

IP.com Disclosure Number: IPCOM000062396D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Emma, PG Knight, JW Pomerene, JH Rechtschaffen, RN Sparacio, FJ [+details]

Abstract

In a MP system whose CPUs have a store in cache algorithm, a cache line whose contents have been stored into by the CPU contains the only copy of the data for the MP system. In the event a second CPU requires access to the data, the line must be transferred from the first to the second CPU. In some present systems this is done over a separate "line castout bus". The requesting CPU initiates a request to main memory for the line and the storage control unit (SCU) fields this request and activates both a request to main memory and an interrogation of the other CPU's cache contents. If the line is in the other CPU's cache and modified, then the request to main memory is cancelled and the line is transferred via the "line castout bus," one doubleword (DW) per cycle. This takes 16 cycles for a typical system.