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Dynamic Random-Access Memory Sense Amplifier Latch Set Circuit

IP.com Disclosure Number: IPCOM000062397D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Nickel, DJ [+details]

Abstract

A dynamic random-access memory (DRAM) sense amplifier (SA) latch set circuit optimizes latch set time to insure maximum signal amplification, and the mechanism is self regulating. When a latch set pulse for a DRAM sense amplifier latch circuit is turned on too soon, the signal will be lost in the DRAM. If the latch set pulse is too late, time will be lost. By introducing an interlock feature to the SA latch set mechanism, the DRAM SA latch set pulse timing will be optimized. Shown in the figure is a schematic of a SA data latch set circuit 20, data latches 21 and a SA node X line which is common to the bottom of data latches 21 and a data latch's set monitor transistor Tx. The function of the SA latch set circuit is to discharge the heavily loaded SA node X line in a precisely controlled two-step sequence.