High Resolution Enhancement for an On-Chip Variable Strobe-Timing Generator
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
An enhancement is proposed to a technique to simplify the external timing requirements for high performance arrays used in semiconductor bipolar gate arrays. An improved logic/layout design is proposed which offers multiple selectable paths with identical logic blocks that have various capacitive loads yielding delay differences less than a logic block delay. In a previous work [*] a technique was developed to measure the access time of high performance embedded arrays. This used an on-chip variable strobe-timing generator with one technology block delay resolution. This proposal enhances the design so that the resolution of the variable clock strobe is less than one technology block delay. A diagram of the proposed circuit which will increase the resolution of the variable clock strobe is given in Fig. 1.