Browse Prior Art Database

Word Line Detector Circuit

IP.com Disclosure Number: IPCOM000062414D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Ellis, W Fifield, J Nguyen, Q [+details]

Abstract

This article describes a random-access memory (RAM) circuit which optimizes the timing between word line select and signal amplification. Conventional methods of selecting a sense amplifier (S/A) at the appropriate time after the word line (WL) select rely on a word line delay compensation circuit to accommodate the worst-case cell delay or a sample word line circuit to simulate (track) the rise time of the actual word line. An ideal method of selecting a S/A for optimum performance is to use the actual physical word line (PWL) or reference word line (RWL) to trigger the S/A timing clocks. The use of a RWL for tracking rather than a WL is preferred because the number of RWLs is substantially less than that of the actual WLs. One RWL and one WL in a cell array will be driven high at a time.