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Improved Specimen Preparation for Shallow Junction Spreading Resistance Measurements

IP.com Disclosure Number: IPCOM000062419D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Halbach, RE [+details]

Abstract

A technique for preparing a field-effect transistor (FET) shallow junction spreading resistance measurement specimen is described. This technique reduces measurement noise, improves measurement starting point resolution, and minimizes early junction point detection errors. A new two-step polishing technique to form a shallow junction spreading resistance specimen 10, as shown in Fig. 1, produces a smooth beveled measurement surface 11. A clear intersection 12 is visible between surfaces 11 and 13. The well-defined intersection 12 results in a more definitive measurement starting point. The initial beveled surface polishing step (rough grind) is done using a rough soda-lime glass surface mounted on a turntable which is rotated slowly.