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Heterostructures With Self-Aligned Trenches

IP.com Disclosure Number: IPCOM000062470D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Frank, DJ Knoedler, CM Wright, SL [+details]

Abstract

Self-aligned isolation trenches may be formed, separating specific regions in a semiconductor layer, by providing a reactive ion etch (RIE) resistant pattern above the layer and an RIE resistant layer on the surface of the semiconductor layer. The composite is then etched in an ambient that will not etch the surface protection layer, but will etch the pattern layer slowly and the semiconductor rapidly. When the semiconductor is GaAs, the pattern layer may be Mo, the surface protection layer may be formed when FREON 14* and oxygen are used to etch the Mo, and the trench forming etch may be FREON 12 and helium. An RIE resistant layer, such as AlGaAs, may also be used between the semiconductor layer and the substrate, if desired. The structure is shown in Fig 1.