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Dynamic Burn-In of Integrated Circuit Chips at the Wafer Level Disclosure Number: IPCOM000062472D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

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Related People

DeLuca, BF Watson, KM [+details]


By fabricating a wafer with special test circuitry in the kerf area which is driven by conductor lines extending to pads around the perimeter of a wafer, each chip on the wafer is dynamically burned-in prior to wafer dicing. Integrated circuits (ICs) shipped to customers in the unmounted chip format benefit from a technique which allows for burn-in at the wafer level prior to dicing as well as a cost-saving technique over module burn-in methods. The kerf area between the active chips is utilized to fabricate test circuitry. Counters and voltage toggling circuits are used to dynamically exercise chip inputs. Each chip and its test circuitry are driven through conductors extending to pads located around the perimeter of a wafer. Power lines have multiple pads on the wafer perimeter to carry the load currents required.