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Model for Delta-I Correction

IP.com Disclosure Number: IPCOM000062473D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Hickson, JB Hokenek, E Kurtzberg, JM Roth, JP [+details]

Abstract

This article describes a method for correcting current distribution in some types of electrical networks. The method is applicable to the design of many types of integrated circuit chips, wafers, cards, boards and other electrical packages. The basic problem addressed is often known by the name "Delta-I". Assume some purely resistive electrical network is embedded in an integrated circuit chip design, with all current sources external to the chip and beyond the boundaries of the network. Standard equations can be used to evaluate the currents flowing in all branches of the network. Some of these currents may be considered "excessive", or beyond some desired limit. The chip wiring design can be modified to increase resistance within specific branches of the network. Where resistance is increased, the current is decreased.