In-Line Reliability Limited Yield
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
The method described here is an extension of the concept described in U.S. Patent 3,751,647, which emphasizes photo limited yield (PLY) modeling. A reliability test limited yield (RTLY) is created, utilizing electrical test data taken at progressive stages of device processing and packaging, to project failure probability. Thus, a semiconductor manufacturing line control is established to attain high reliability required of very large-scale integration (VLSI) circuits. VLSI product is normally tested on wafers ("Post-metallization probe"), at the device level, deck level of assembly, post burn-in, and final module test. RTLY data is taken at each of the normal test levels. For RTLY determination, the product is tested outside of the normal test window in increasing increments of voltage on any of several voltage parameters.