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Optimized Logic Layout Using SGP Technology

IP.com Disclosure Number: IPCOM000062482D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Bechade, RA [+details]

Abstract

Utilization of horizontal and vertical metal lines to interconnect internal nodes of logic functions will enhance circuit layout densities in the silicon gate process (SGP). The layout of any two-level logic function in the SGP technology can be optimized where the first level of logic is composed of more than one adjacent logic block and the second level of logic is a function of the first level logic blocks. The internal nodes of the first level logic blocks can be connected with vertical metal lines (first level metal), and the internal nodes of the second level logic can be connected with horizontal metal lines (second level metal). Fig. 1 shows a two-level random logic block diagram with inputs A through H, and Fig. 2 shows a physical layout of the logic block diagram.