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FET Decoder Tree Layout for Speed Improvement

IP.com Disclosure Number: IPCOM000062484D
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Houghton, RJ [+details]

Abstract

This article relates to a FET (field-effect transistor) decoder circuit design allowing a layout technique in silicon which enhances the capacitive drive output capability without additional input drive requirements or silicon area. Improved speed through additional drive capability with no additional silicon required for layout can be realized when a tree-style arrangement of FET decoder devices is used rather than a conventional NAND approach. Fig. 1a shows a conventional NAND decoder. Fig. 1b is the physical layout of the NAND devices in silicon. A diffusion region 10 is associated with each device source/drain, and a device gate 11 is associated with each address input, i.e., A0, A0 not, A1, A1 not,...etc. All levels of the serial-connected devices, shown in Fig. 1a, have a gate width of W.