Method for Minimizing Within-Chip Registration Error
Original Publication Date: 1986-Nov-01
Included in the Prior Art Database: 2005-Mar-09
A method is described for minimizing within-chip overlay errors when a mix of stepping reduction photo exposure tools (P1) and one-to-one scanning photo exposure tools (P2) are used in semiconductor circuit fabrication. This method uses capabilities already incorporated in P1 and P2 tools to compensate for magnification and skew overlay differences found to exist within-chip images formed by the two tools. First, the amount and sign of magnification difference is determined. The error is then compensated by adding an appropriate increment (of sign opposite to that of the magnification error) to the P1 step magnitude in both horizontal and vertical directions.