Static Random-Access Memory Cell
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
A static four-device random-access memory (RAM) cell layout is described in which adjacent cell-pairs are symmetrical about a vertical axis and each cell has electrical and rotational symmetry about a central point. Separated placement of bit lines reduces capacitance between bit lines, thus increasing signal and performance of the cell. Another performance improvement is achieved by incorporating split word lines in the layout. Buried contacts are placed in the layout such that their contact resistance is in series with gates only, not with active current paths. This cell provides wiring to carry supply voltage Vdd to polysilicon load resistors. Thus, a mask level and an ion implantation process step usually required to form polysilicon connecting lines between Vdd and polysilicon load resistors are avoided. Fig.