Browse Prior Art Database

Mosfet on Chip Timer Utilizing Device Conduction Near Threshold for Long Delay

IP.com Disclosure Number: IPCOM000062507D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Cranford, HC Garvin, SJ [+details]

Abstract

This article describes an on-chip timer circuit which provides a pulse train with fairly long down-time (example: approximately 1 millisecond) and fairly short up-time. The circuit is fabricated from enhancement- and depletion-type FETs (field-effect transistors). The circuit utilizes device conductance in the near threshold region to obtain long timing intervals between pulses. In this region, only a very small amount of current is needed to provide a long discharge time. With reference to the figure, the output is a pulse train at node X9 which follows (that is, controlled by) node TX9. The small currents are generated by biasing the gates of devices 15 and 20 slightly above their respective threshold voltages (Vth).