Browse Prior Art Database

Power-On Reset Circuit

IP.com Disclosure Number: IPCOM000062516D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Beers, GE Frankeny, RF [+details]

Abstract

The figure illustrates an attachment circuit for a peripheral device to insure the generation of a system power on reset (POR) signal when the peripheral device is connected to the system and which can insure that no damage is sustained by the device when the connection is made. The portion 10 of the interface comprises a ground connector 11, a 'log power on reset' connector 12 and a power connector 13. It does not matter which connector 11, 12 or 13 makes contact first because the circuit will still generate a POR signal of the same duration. For example, assume that connector 13 is made first, connector 11 is made next and connector 12 is made last. Since connector 13 and connector 11 are applied first, there is no special problem.