Browse Prior Art Database

Bus Charge Level Control Circuit

IP.com Disclosure Number: IPCOM000062529D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Chao, HH Tsai, MY [+details]

Abstract

This article relates generally to VLSI (very large-scale integration) chip design and, more particularly, to data transfer among a plurality of macros along a common bus. A data bus common to a plurality of macros can be used during data transfer by employing active pull-up or pull-down devices to precharge and to maintain subsequent bus data charge. Referring to Fig. 1, macros 1 and 2, among a plurality, are connected to common bus 3 which is, in turn, connected to pull-up and pull-down devices within the broken line 4. Data transfer to and from the bus requires three clock phases: Phase PRE, Phase Out and Phase In. During Phase PRE, transistor 5 is turned on at its gate to precharge the bus to Vdd, since it is difficult for the macros to drive the whole bus up.