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Hidden Dynamic RAM Refresh for Use With Synchronous DMA Controllers and Asynchronous Dynamic RAM Controllers

IP.com Disclosure Number: IPCOM000062547D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Buckton, WL Schwartz, AJ [+details]

Abstract

Many currently available direct memory access (DMA) controllers require that data be valid synchronous to the DMA operations. When using dynamic random-access memories (RAMs) which require refresh, refresh cannot be allowed to occur during the direct memory access cycle because of the synchronous valid data requirement. For a two megabit serial data rate, the DMA cycle typically takes one microsecond every four microseconds. The first 500 nanoseconds of the DMA cycle is setup time with data transfer occurring on the second half of the cycle. By forcing a refresh every time a DMA cycle is requested, the refresh overlaps with the first half of the DMA cycle. This operation causes the refresh to be synchronous to the DMA cycle and guarantees RAM availability when the DMA controller raises a transfer signal.