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Cascode Voltage Switch for Cmos Logic

IP.com Disclosure Number: IPCOM000062593D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Hanafi, HI Peterson, CW [+details]

Abstract

This article relates generally to logic circuit switching and, more particularly, to improving switching speed by separation of the logic tree from its output nodes. Retention time, soft error exposure, race conditions and noise sensitivity can be alleviated in cascode logic switching by using a depletion device with grounded gate to isolate the output node from the tree branches. Referring to Fig. 1, T1 and T2 are p-channel devices and T3, T4, TA and TAN are n-channel devices. Assume all inputs to branches A and B of the logic tree are at high potential VH except devices TA and TAN whose inputs are controlled by signals SA and SAN, respectively. If input SA is low, node C is at VH, node B is at -VTD, where VTD is the depletion device threshold, and node CN is at ground. Thus, devices T1 and T2 are, respectively, on and off.