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Speed Enhancement Technique for Current Switch Circuits Disclosure Number: IPCOM000062608D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

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Chan, YH [+details]


The circuit technique disclosed in this article employs the intrinsic device capacitance of an inverse transistor for effective speed enhancement of a current switch circuit. The disclosed technique is simple to implement, costs nothing in power, chip area or layout complexity, and can be readily applied to improve the speed-power products of most CSEF (current-switch emitter-follower) circuits. (Image Omitted) A conventional CSEF inverter circuit is shown in Fig. 1. Circuit delay is determined by two factors: 1) power level (i.e., Ic), and 2) device speed (i.e., Ft and b of the NPN transistors T1, T2, and T3). For a given device type and a fixed current level, an external capacitor C (see dotted line) is sometimes added to the common emitter node 2 to improve the AC performance of this design.