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Three-Level Decoding Scheme for High Density Arrays Disclosure Number: IPCOM000062626D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

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Wong, RC [+details]


A method has been proposed to reduce the area and power required by decoders of large arrays in semiconductor devices. It provides for emitter dotting of the true-complement generator outputs along with a matrix decode. (Image Omitted) For high density arrays it is common to use two-level decoding schemes. These include transistor-transistor logic (TTL) and emitter- coupled logic (ECL) decoders. This proposal suggests a three-level decoding scheme to further minimize the power, delay and area required for dense arrays (for example, cell count > 80 Kbits). _ The circuitry in Fig. 1 is for a low wordline down swing and for a relatively low input level. If higher levels are used, some ground voltage sources may be replaced with current sinks, as indicated in Fig. 2.