Clock Chopper for Complementary-Transistor Switch Arrays
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09
This article describes an efficient circuit means to perform on-chip pulse generation, thereby simplifying array system timing requirements. A single-level clock chopper circuit [*] has been designed for complementary transistor switch (CTS) random access memories (RAMs). It offers the advantages of low complexity (only 3 additional circuits) (Image Omitted) and minimal chip access penalty when compared with a two-level design. From an external system clock, it will generate an on-chip regulated gate pulse to control the chip select/deselect functions. The clock chopper logic has an enable/disable input which allows the chip to be operated in either clock chopper mode or conventional non-chopper mode. A test output is also included for chip characterization purposes at final test. Fig.