Browse Prior Art Database

Pipelined Memory Array Chip

IP.com Disclosure Number: IPCOM000062656D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
DeLuca, BF [+details]

Abstract

By the use of a master/slave (M/S) latch pipeline which advances data from one segment of a memory chip operation cycle to a next segment of the cycle at each cycle of a master chip clock, data transfer speed can be enhanced by a factor of 4 once the pipeline is filled with instructions. Array access is segmented into four segments: 1) receive array address (A/A), 2) generate true/complement (T/C) drive for a selected cell, 3) sense and latch cell data, and 4) drive data off chip. Data is put into a master latch at a leading edge of a clock pulse, and data is transferred into a slave latch at a trailing edge of a clock pulse. This master chip clock drives only the M/S latches and is not shown in the diagram.