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Alteration of Threshold Voltage of Enhancement Field-Effect Transistors

IP.com Disclosure Number: IPCOM000062675D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Abadeer, WW LeBlanc, AR [+details]

Abstract

Controlled amounts of trapped positive charge (holes) in standard SiO2 gate insulator alters threshold voltage (Vt) of enhancement field-effect transistors (FETs). By applying controlled amplitude current pulses while a gate insulator field exceeding a critical value (Ec = approximately 6 megavolts per centimeter) is applied, trapped charges are created in a controlled manner. The Vt of the device may be measured between current pulses to detect achievement of desired Vt level. A standard high Vt enhancement transistor can be operated as a low Vt, zero Vt, or depletion device by trapping appropriate charge levels. The figure shows the change in Vt of an enhancement transistor resulting from applying a series of 1 microamp current pulses while a field exceeding Ec is applied.