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Multi-Port Latch-Trigger SRL Circuit With Automatic Reload Feature

IP.com Disclosure Number: IPCOM000062684D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Ng, SK Nosowicz, EJ [+details]

Abstract

A circuit is provided that compensates for late system clock arrival in a multi-port shift register latch (SRL). As seen in Fig. 1, a typical logical implementation of a multi-port SRL has two polarity hold latches L1, L2, and a two port latch 1, 2. When the system clock (SC) is in a logical true state and the gate line for port 1 (G1) is activated, the input data (D1) becomes the content of the L1 latch until changed by the proper combination of inputs. Similarly, data port 2 can transfer data into L1 by activating SC and G2. The T line is used to transfer data from L1 to L2. Although Fig. 1 represents a two-port design, it can be generalized to an N port structure. The type of system clocking used in a latch-trigger design is seen in Fig. 2.