Browse Prior Art Database

Hardware Cache Simulator for Desktop S/370

IP.com Disclosure Number: IPCOM000062695D
Original Publication Date: 1986-Dec-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Erhard, JJ Laubli, GW Stevens, JD Sucher, DJ Walk, BM [+details]

Abstract

One method of increasing performance on mainframe and minicomputers has been to implement a cache memory as a small, high speed memory array between the processor and slower main memory. As the demand for desk- top processing power increases, the addition of a cache memory to microprocessor-based workstations, such as the Personal Computer AT/ 370, becomes attractive. Traditionally, software simulation has been employed to quantify the performance gain provided by using a cache memory. One alternative that retains the versatility of a software simulation model, yet provides a more accurate measurement of the increase in system throughput, is a general-purpose Hardware Cache Simulator. A Hardware Cache Simulator can simulate many different sizes of cache memory, varying in both width and number of entries.