Browse Prior Art Database

LSSD SRL Analyzer

IP.com Disclosure Number: IPCOM000062810D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Fiedler, TS Lee, VS [+details]

Abstract

Very large-scale integration (VLSI) has imposed a severe limitation on the accessibility of circuits internal to a module. Specifically, the states of the latches in a VLSI module are generally not observable. This article describes an analyzer that uses the Level Sensitive Scan Design (LSSD) concept to provide a means of stopping a machine at any given time specified by the user, and observing the states of the shift register latches (SRLs) internal to a module. A word recognizer 11 captures the triggering events 12 for the analyzer. The triggering signals could be the failing event(s), some interrupt lines or a microprocessor instruction address.