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Silicon-On-Insulator Processes for FET and Bipolar Devices

IP.com Disclosure Number: IPCOM000062815D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Silvestri, VJ [+details]

Abstract

These processes form fully isolated epitaxial silicon growth regions used to build FET, bipolar and MOS-FET integrated circuits on silicon substrates. Process for Building Isolation Structure Holes are formed in SiO2 oxide layer of silicon wafer by conventional, known processes (Fig. 1). Silicon is epitaxially deposited and allowed to significantly over-grow the SiO2 layer (Fig. 2). SiO2 layer is stripped-away, exposing growth stem linkage to silicon substrate (Fig. 3). Re-oxidize so that stem is entirely oxidized away. Epitaxial growth is now electrically isolated from silicon substrate (Fig. 4). Chemical-vapor-deposited (CVD) polysilicon nucleation layer is deposited (Fig. 5), and high-temperature polysilicon refill applied. Substrate is planarized using reactive ion etch or mechanical polishing by known processes (Fig. 6).