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High-Current Field-Effect Transistor

IP.com Disclosure Number: IPCOM000062829D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Jambotkar, CG [+details]

Abstract

The process describes the manufacture of field=effect transistors (FETs) capable of carrying several amperes of current for a given chip area. This is facilitated by minimizing the chip area occupied by gate electrodes, thus maximizing the channel area through which current flows from source to drain. The gate electrodes are formed by compact, polysilicon-filled isolated trenches no leakage from source or drain to gate. In Fig. 1, a lightly doped N-epitaxy 11 is formed above N+ 10 substrate. SiO2 12 is formed at the epitaxial surface, followed by formation of recessed SiO2 12. In Fig. 2, a layer of N+ 20 is formed at the epitaxial surface. Trenches are formed, as illustrated. In Fig. 3, a dielectric layer SiO2 12 is formed at the trench walls where thickness is governed by the device characteristics.