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E-Level Test Bed Three-Plate Anode Design for Silicon Etching

IP.com Disclosure Number: IPCOM000062831D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Giammarco, NJ Kaplita, GA [+details]

Abstract

The disclosed three-plate anode configuration, used in dry silicon etching, reduces the effect of silicon loading, decreases plasma potential, and achieves uniformity. The use of a dual-plate anode configuration in an E-level test bed system for silicon etching produces a relatively low cathode voltage very sensitive to silicon loading. A slight variation in silicon loading produces a voltage shift of a few volts which is a large percentage of the nominal voltage. This causes the formation of "black silicon" and isotropic etching, creating a very narrow process window for silicon etching. The disclosed process utilizes a third plate under the dual-plate anode. This plate is fully perforated (holes one quarter inch in diameter or greater), extends the full circumference of the chamber, and is at ground potential.