Browse Prior Art Database

Means for Executing Register-To-Register Instructions in a Computer With a Single-Port Local Store

IP.com Disclosure Number: IPCOM000062837D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Olnowich, H Vandling, G [+details]

Abstract

In general-purpose computers with storage operand prefetch, Register-to-Register (RR) instructions inherently execute in approximately the same amount of time as their corresponding Storage-to-Register (RX) instructions. In a pipelined design which has a two-port local store, the cycle used for effective addressing for an RX instruction is unused for a corresponding RR instruction. When an Arithmetic and Logic Unit (ALU) with a single-port local store is used, the storage operand is prefetched and the first operand can be fetched from the local store, allowing RX instruction execution with no problem. A method to fetch a second register operand, without requiring additional time, is to prefetch the second register operand in advance during the time slot corresponding to the Effective Address (EA) slot for an RX instruction.